View ATSAM2533_4284500.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Single Chip Synthesizer + Effects, Typical Application Includes:
- Wavetable Synthesis, Serial Midi In & Out, Parallel MIDI - Effects: Reverb + Chorus, on MIDI and/or Audio In - Surround on 2 or 4 Speakers with Intensity/Delay Control - Equalizer: 4 Bands, Parametric - Audio-In Processing through Echo, Equalizer, Surround Low Chip Count - Synthesizer, ROM/Flash, DAC - Effects RAM is Built-in (32K x 16) Low Power - 23 mA Typ. Operating - Single 3.3V Supply - Built-in 1.8V Regulator with Power Down Mode High Quality Wavetable Synthesis - 16-bit Samples, 48 kHz Sampling Rate, 24 dB Digital Filter per Voice - Up to 64 Voices Polyphony - Up to 16 Mega x 16 ROM for Firmware, and PCM Data Available Wavetable Firmware and Sample Sets - CleanWave8 Low Cost General MIDI 1 Megabyte Firmware + Sample Set - CleanWave32 High Quality 4 Megabyte Firmware + Sample Set - CleanWave64 Top Quality 8 Megabyte Firmware + Sample Set - Other Sample Sets Available under Special Conditions Fast Product to Market - Enhanced P16 Processor with C Compiler - Built-in ROM Debugger - Flash Programmer through Dedicated Pin Small Footprint - 14 x 14 mm, 0.5 mm Pitch, 100-lead LQFP Package Typical Applications - Portable Telephones - Computer Karaokes, Portable Karaokes - Keyboards, Portable Keyboards Instruments
*
*
Audio Processing ATSAM2533 Low-power Synthesizer with Effects and Built-in RAM
*
*
*
* *
1. Description
The ATSAM2533 is a low cost derivative of the ATSAM97xx series. It retains the same high quality synthesis with up to 64 voices polyphony. The ATSAM2533 maximum wavetable memory is 32 MBytes and the parallel communication is through a standard 8-bit port. The integrated 32K x 16 RAM allows for high quality effects without additional components. The highly integrated architecture from ATSAM2533 combines a specialized high performance RISC-based digital signal processor (Synthesis/DSP) and a general purpose 16-bit CISC-based control processor on a single chip. An on-chip memory management unit (MMU) allows the synthesis/DSP and the control processor to share external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the 8-bit parallel, the on-chip MIDI
6396A-DRMSD-15-Oct-08
UART, and the CODEC control interface, with minimum intervention from the control processor.
2. ATSAM2533 IC Architecture Block Diagram
Figure 2-1. ATSAM2533 IC Architecture Block Diagram
Synthesis/DSP 64 Slots RISC DSP Core Includes: 512 x 32 Alg RAM 128 x 28 MA1 RAM 256 x 28 MA2 RAM 256 x 28 MB RAM 256 x 16 MX RAM 256 x 12 MY RAM 64 x 13 ML RAM CODEC + DAC
P16 Processor
32K x 16 RAM
16-bit CISC Processor Core includes 256 x 16 Data RAM
MMU Memory Management Unit ROM or Flash
I/O Functions Includes Control/Status MIDI USART Timers CODEC Data I/F Host I/F FIFO ATSAM2533
ROM Debug/Flash Prog MIDI 8-bit Port Debug Flash Prog
2
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
3. Functional Description
3.1 Synthesis/DSP Engine
The synthesis/DSP engine operates on a frame timing basis with the frame subdivided into 64 processes slots. Each process is itself divided into 16 micro-instructions known as an "algorithm" Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical application will use half the capacity of the synthesis/DSP engine for synthesis, thus providing state of the art 32-voice wavetable polyphony. The remaining processing power will be used for typical functions like reverberation, chorus, audio in processing, surround effect, equalizer, etc. Frequently accessed synthesis/DSP parameter data are stored into 5 banks of on-chip RAM memory. Sample data or delay lines, which are accessed relatively infrequently are stored in external ROM or internal 32K x16 RAM memory. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS). Separate busses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to 6 simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 300 million operations per second (MOPS).
3.2
Enhanced P16 Control Processor and I/O Functions
The Enhanced P16 control processor is the new version of P16 processor with added instructions allowing C compiling. The P16 control processor is a general purpose 16-bit CISC processor core, which runs from external memory. It includes 256 words of local RAM data memory. The P16 control processor writes to the parameter RAM blocks within the synthesis/DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the parallel 8-bit interface and then controls the Synthesis/DSP by writing into the parameter RAM banks in the DSP core. Slowly changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the parallel 8-bit interface through specialized "intelligent" peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16. The parallel 8-bit interface is implemented using one address lines (A0), a chip select signal, read and write strobes from the host and an 8-bit data bus (D0-D7). Karaoke and keyboard applications can take advantage of the parallel 8-bit interface to communicate with the ATSAM2533 at high speed, with the MIDI IN and MIDI OUT signals remaining available.
3
6396A-DRMSD-15-Oct-08
3.3
Memory Management Unit (MMU)
The Memory Management Unit (MMU) block allows external ROM/Flash and/or internal 32K x 16 RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows a single device (i.e. internal RAM) to serve as delay lines for the synthesis/DSP and as data memory for the P16 control processor.
4. Typical Design Applications
4.1 Portable Telephone
Figure 4-1. Portable Telephone
CleanWave ROM
ATSAM2533
DAC or CODEC
General MIDI Compliant Wavetable Synthesis RISC DSP Core Parallel or Serial Interface Reverb + Chorus Surround Effect 4 Bands Parametric Equalizer Audio In Effects (CODEC Required)
4.2
Low Cost Karaoke, Hand-held Karaoke
Figure 4-2. Low Cost Karaoke, Hand-held Karaoke
CleanWave ROM
ATSAM2533
CODEC
General MIDI Compliant Synthesis Sound Extension (CleanWave64) Reverb + Chorus MIDI Serial or 8-bit Parallel Interface 4 Channels Surround (Requires Extra DAC) 4 Bands Parametric Equalizer Microphone Echo
4.3
Low Cost Keyboard Instrument
Figure 4-3. Low Cost Keyboard Instrument
CleanWave ROM
ATSAM2533
DAC
General MIDI Compliant Synthesis Sound Extension (CleanWave64) Reverb + Chorus MIDI Serial or 8-bit Parallel Interface Surround Effect 4 Bands Parametric Equalizer
4
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
5. Pinout
5.1 Pin Description by Function 100-pin LQFP Package
* 5VT indicates a 5 volt tolerant input or i/O pin.
Table 5-1.
Name GND
ATSAM2523 Pinout by Name
Pin# 1, 12, 26, 41, 51, 69, 76, 77, 84 79 13, 25, 33, 42, 50, 59, 68, 75, 83, 100 TYPE PWR Function Power ground - all GND pins should be returned to digital ground Power for the internal PLL, + 1.8V nominal (1.8V 10%). These pins can be connected to the output of the regulator OUTVC18 (pin 34). A 100 nF decoupling capacitor should be connected between this pin and PLL ground (pin77)
VD18
PWR
VD33
PWR
Periphery power + 3V to 3.6V. All VD33 pins should be returned to nominal +3.3V.
OUTVC18
34
PWR
3.3V to 1.8 V regulator output. The built-in regulator gives 1.8V for internal use (core supply). PLL supply pin VD18 could also be connected to this pin. Decoupling capacitors 470pF in parallel with 2.2 or 4.7F must be connected between OUTVC18 and GND. 8 bit data bus to host processor. Information on these pins is parallel MIDI Chip select from host, active low. Write from host, active low. Read from host, active low. Select address of slave 8-bit interface registers: 0: data registers (read/write) 1: status register (read) control register (write) This pin has a built-in pull down. Slave 8bit interface interrupt request. High when data is ready to be transferred from chip to host. Reset by a read from host (CS/=0 and RD/=0) Master reset input, active low. Crystal connection. Crystal frequency should be Fs * 256 (typ 12.288 MHz) Xtal frequency is internally multiplied by 4 to provide the IC master clock. An external 12.288 MHz clock can also be used on X1 (Analog or 3.3V CMOS logic). X2 cannot be used to drive external ICs, use CKOUT instead. Buffered X2 output, can be used to drive external DAC master clock (256 * Fs) Two stereo serial audio data output (4 audio channels). Each output holds 64 bits (2 x 32) of serial data per frame. Audio data has up to 20 bits precision. Audio data bit clock, provides timing to DABD0-1, DAAD. Audio data word select. The timing of WSBD can be selected to be I2S or Japanese compatible. Stereo serial audio data input. General purpose programmable I/O pins. These pins have a built-in pull down.
D0-D7 CS WR RD
4-11 2 99 3
I/O 5VT IN 5VT IN 5VT IN 5VT
A0
98
IN 5VT
IRQ RESET
97 82
OUT IN 5VT
X1,X2
80, 81
-
CKOUT DABD0-1 CLBD WSBD DAAD P0-P3
88 91, 92 89 90 93 49, 52-54
OUT OUT OUT OUT IN 5VT I/O 5VT
5
6396A-DRMSD-15-Oct-08
Table 5-1.
Name DBCLK DBDATA DBACK MIDI IN MIDI OUT
ATSAM2523 Pinout by Name (Continued)
Pin# 85 87 86 96 94 35-40, 43-48, 55-58, 60-67 14-24, 27-31 70 72 71 95, 78 TYPE IN 5VT I/O 5VT OUT IN 5VT OUT Function Debug clock, should be connected to VD33 under normal operation. If DBCLK is found low just after RESET, then the internal ROM debugger/Flash programmer is started Debug data, allows serial communication for debug/Flash programming. This pin has a builtin pull down. Debug ack, toggled each time a bit is received/sent on DBDATA MIDI IN, input. This pin has a built-in pull up. MIDI OUT, output.
WA0-23
OUT
External memory address (ROM/Flash). Up to 32 Mega bytes.
WD0-15 WCS WWE WOE TEST0-1
I/O 5VT OUT OUT OUT IN
External ROM/Flash data. External ROM/Flash chip select, active low. External Flash write enable, active low. External ROM/Flash output enable, active low. Test pins, should be returned to GND. Power down, active low. When power down is active, WCS, WWE, WOE, address and data lines are floated. All other outputs are set to 0. The crystal oscillator is stopped, OUTVC18 is set to 0 and 1.8V supply voltage is removed from the core. To exit from power down, PDWN must be set to VD33, then RESET applied. When unused this pin must be connected to VD33. Not connected pins.
PDWN
32
IN
NC
73, 74
-
6
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
5.2 Pinout by Pin Number
ATSAM2523 Pinout by Pin Number
Signal Name GND CS RD D0 D1 D2 D3 D4 D5 D6 D7 GND VD33 WD0 WD1 WD2 WD3 WD4 WD5 WD6 WD7 WD8 WD9 WD10 VD33 Pin# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name GND WD11 WD12 WD13 WD14 WD15 PDWN VD33 OUTVC18 WA0 WA1 WA2 WA3 WA4 WA5 GND VD33 WA6 WA7 WA8 WA9 WA10 WA11 P0 VD33 Pin# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name GND P1 P2 P3 WA12 WA13 WA14 WA15 VD33 WA16 WA17 WA18 WA19 WA20 WA21 WA22 WA23 VD33 GND WCS WOE WWE NC NC VD33 Pin# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name GND GND TEST1 VD18 X1 X2 RESET VD33 GND DBCLK DBACK DBDATA CKOUT CLBD WSBD DABD0 DABD1 DAAD MIDI_OUT TEST0 MIDI_IN IRQ A0 WR VD33
Table 5-2.
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
7
6396A-DRMSD-15-Oct-08
6. Marking
FRANCE
SAM2533
YYWW 58A66C XXXXXXXXX
Pin 1
7. Mechanical Dimensions
Figure 7-1. 100-lead Quad Flat Pack (LQFP100)
8
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
8. Electrical Characteristics
8.1 Absolute Maximum Ratings(*)
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages with respect to 0V, GND = 0V.
Temperature under bias................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on any 5 volt tolerant pin .......................... -0.3 to 5.5V Voltage on any non 5 volt tolerant pin ........ -0.3 to VD33 + 0.3V Supply Voltage.......................................................................... VD33 ......................................................................-0.3V to 3.6V VD18 .........................................................................-0.3V to 2V Maximum IOL per I/O pin............................................... 10 mA Maximum IOH per I/O pin .............................................. 10 mA Maximum Output current from OUTVC18 pin (max duration = 1sec) IREGO ........................................................................... 70 mA
9
6396A-DRMSD-15-Oct-08
8.2
Recommended Operating Conditions
Recommended Operating Conditions
Parameter Supply voltage Supply voltage (PLL) OUTVC18 output current Operating ambient temperature Min 3 1.65 -25 Typ 3.3 1.8 30 70 Mx 3.6 1.95 Unit V V mA C
Table 8-1.
Symbol VD33 VD18 IREGO TA
8.3
DC Characteristics
DC Characteristics (TA = 25C, VD33 = 3.3V 10%, VD18 = 1.8V 10%)
Parameter Low level input voltage High level input voltage on 5VT pins High level input voltage on non-5VT pins Low level output voltage IOL=4mA High level output voltage IOH=4mA Power supply current at (crystal freq.=12.288 MHz) Min -0.3 2 2 VD33-0.4 Typ 0.7 22 Power down supply current Pull-up or Pull-down resistor 8 0.6 13 25 Mx 0.8 5.5 3.6 0.4 Unit V V V V V mA mA mA kOhm
Table 8-2.
Symbol VIL VIH VIH VOL VOH ID18 ID33 - Rud
10
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
9. Timings
All timing conditions: VD33 =3.3V, VD18 =1.8V, TA = 25C, all outputs except X2 have load capacitance = 30 pF. All timings refer to tck, which is the internal master clock period. The internal master clock frequency is 4 times the frequency at pin X1. Therefore tck = txtal/4. The sampling rate is given by 1/(tck*1024). The maximum crystal frequency/clock frequency at X1 is 12.288 MHz (48 kHz sampling rate).
9.1
Crystal Frequency Selection Considerations
There is a trade-off between the crystal frequency and the support of widely available external ROM/Flash components. Table 9-1 allows to select the best fit for a given application; Table 9-1. Crystal Frequency Selection Chart
Xtal (MHz) 12.288 11.2896 9.60 8.00 tck (ns) 20.35 22.14 26.04 31.25 ROM tA (ns) 92 101 120 146
Sample Rate (kHz) 48 44.1 37.5 31.25
Using 12.288 MHz crystal frequency allows to use widely available ROM/Flash with 90 ns access time, while providing state of the art 48 kHz sampling rate.
9.2
9.2.1
PC Host Interface
Timings Host Interface Read Cycle
Figure 9-1.
A0 tavcs CS/ RD/ tcslrdl tprd trdhcsh
trdldv D0-D7
tdrh
11
6396A-DRMSD-15-Oct-08
Figure 9-2.
Host Interface Write Cycle
twrcyc
A0 tavcs CS/ tcslwrl WR/ tdws D0-D7 tdwh tpwr twrhcsh
Table 9-2.
Symbol tavcs tcslrdl trdhcsh tprd trdldv tdrh tcslrwrl twrhcsh tpwr tdws tdwh twrcyc
Timing Parameters
Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time Write cycle Min 0 5 5 50 5 5 5 50 10 0 128 Typ Mx 20 10 Unit ns ns ns ns ns ns ns ns ns ns ns tck
9.2.2
7 TE
IO Status Register
6 RF 5 X 4 X 3 X 2 X 1 X 0 X
Status register is read when A0 = 1, RD = 0, CS = 0. * TE: Transmit Empty If 0, data from ATSAM2533 to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ. * RF: Receiver Full If 0, then ATSAM2533 is ready to accept DATA from host.
12
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
9.3 External ROM/Flash Timings
RO/Flash Read Cycle
Figure 9-3.
tRC WCS/ tCSOE WA0WA23 tPOE WOE/ tOE WD0WD15 tACE tDF
Table 9-3.
Symbol tRC tCSOE tPOE tACE tOE tDF
External ROM/Flash Timing Parameters
Parameter Read cycle time Chip select low/address valid to WOE low Output enable pulse width Chip select/address access time Output enable access time Chip select or WOE high to input data Hi-Z Min 5*tck 2*tck-5 5*tck-5 3*tck-5 0 Typ 3*tck Mx 6*tck 3*tck+5 2*tck-5 Unit ns ns ns ns ns ns
13
6396A-DRMSD-15-Oct-08
9.4
External Flash Write Timings
External Flash Write Cycle
Figure 9-4.
tWC WCS/ tCSWE WA0WA23 WOE/ tWP WWE/ tDW WD0WD15 tDH
Table 9-4.
Symbol tWC tCSWE tWP tDW tDH
External Flash Write Timing Parameters
Parameter Write cycle time Write enable low from CS or Address or WOE Write pulse width Data out setup time Data out hold time Min 5*tck 2*tck-10 4*tck-10 10 Typ 4*tck Mx 6*tck Unit ns ns ns ns ns
14
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
9.5 Digital Audio Timing
Figure 9-5. Digital Audio Timing
tcw WSBD CLBD DABD0 DABD1 DAAD tsod tsod tcw tclbd
Table 9-5.
Symbol tcw tsod tclbd
Digital Audio Timing Parameters
Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min 8*tck-10 8*tck-10 Typ 16*tck Mx Unit ns ns ns
Figure 9-6.
Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese) CLBD
DABD0 DABD1 DAAD
MSB
LSB (16bits)
LSB (20bits) LSB (18bits)
MSB
Note: * Selection between I2S and Japanese format is a firmware option. * DAAD is 16 bits only.
15
6396A-DRMSD-15-Oct-08
10. Reset and Power-down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take about 20ms. After the low to high transition of RESET, following happens: * The Synthesis/DSP enters an idle state. * P16 program execution starts from address 0100H in ROM space (WCS low). If PDWN is asserted low and VD18 connected to OUTVC18, then the crystal oscillator and PLL will be stopped. The chip enters a deep power down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied.
11. Recommended Crystal Compensation
Figure 11-1. Recommended Crystal Compensation
16
ATSAM2533
6396A-DRMSD-15-Oct-08
ATSAM2533
12. Recommended Board Layout
Like all HCMOS high integration ICs, following simple rules of board layout are mandatory for reliable operation: * GND, VD33, VD18 distribution, decouplings All GND, VD33, VD18 pins should be connected. A GND plane is strongly recommended below the ATSAM2533. The board GND + VD33 planes could be in grid form to minimize EMI. Recommended VD18 decoupling is 0.1 F close to the VD18 pin and 470 pF in parallel with 2.2 or 4.7 F close to OUTVC18 pin. VD33 requires 0.1 uF at each corner of the IC with an additional 10 FT capacitor that should be placed close to the crystal. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors and the ATSAM2533 should be short and shielded. The ground return from the compensation capacitors should be the GND plane from ATSAM2533. * Busses Parallel layout from D0-D7 and WA0-WA23/WD0-WD15 should be avoided. The D0-D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0-WA23/WD0WD15 which can corrupt address and/or data on these busses. A ground plane should be implemented below the D0-D7 bus, which is connected to the host and to the ATSAM2533 GND. A ground plane should be implemented below the WA0-WA23/WD0-WD15 bus, which is connected to the ROM/Flash grounds and to the ATSAM2533. * Analog section A specific AGND ground plane should be provided, which is connected to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the CODEC vendor recommended layout for correct implementation of the analog section.
17
6396A-DRMSD-15-Oct-08
13. Revision History
Table 13-1.
Change Request Ref
Document Ref. 6396A
Comments First issue.
18
ATSAM2533
6396A-DRMSD-15-Oct-08
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com www.atmel.com/Dream Technical Support info@dream.fr Atmel techincal support Sales Contacts www.atmel.com/contacts/
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) 2008 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, DREAM (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
6396A-DRMSD-15-Oct-08

▲Up To Search▲

Price & Availability of ATSAM2533

	To Download ATSAM2533 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .